Electrical isolation between active devices is a requirement for integrated circuits. Electrical isolating structures are formed between active devices to reduce unwanted diffusion of dopants between adjacent devices, to prevent and/or reduce capacitance coupling between adjacent devices, and to prevent latch up (i.e. an unwanted forward biasing of a device from interactions with one or more adjacent devices), to name a few.
Although isolating structures improves the performance and reliability of devices and/or integrated circuits, they typically require a substantial footprint to implement. Since there is a trend to reduce the size of devices and integrated circuits, there is a need to make the size of isolating structures as minimal as possible. One existing isolating structure is an oxide formed by local oxidation of silicon (LOCOS). An undesirable characteristic of LOCOS is that it typically requires a relatively large footprint to properly implement it.
An additional problem with existing isolating structures is that they typically produce a non-planarized top surface in the process of forming these structures. A non-planarized top surface is not desired because subsequent processing on a non-planarized top surface is more difficult than on a planarized surface. Otherwise, an undesirable planarization step is required before subsequent processing is performed. The isolating oxide formed by LOCOS typically results in a non-planarized top surface.
Yet, another problem with existing isolating structures is that they typically have adverse effects due to high temperature processes required to form them. As a result, unwanted diffusion of dopants may occur from the high temperature processes. Additionally, unwanted stresses may form between the isolating structures and other adjacent materials. An example of the effect of a known source of stress in existing isolating structure is the stress caused by the formation of the "bird's beak" at the interface of the LOCOS and adjacent nitride layers.
Thus, there is a need for a method of forming an electrical isolating structure that requires a relatively smaller footprint to implement, that results in a more planarized top surface, that is less susceptible to outgassing and unwanted diffusion, and that produces less stress against adjacent materials. In particular, an improved method of forming a shallow and deep trench isolation is provided herein that reduces or eliminates the problems associated with existing electrical isolating structures for devices and/or integrated circuits.